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The future of ferroelectric field-effect transistor technology - Asif Islam Khan, Ali Keshavarzi and Suman Datta
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The discovery of ferroelectricity in oxides that are compatible with modern semiconductor manufacturing processes, such as hafnium oxide, has led to a re-emergence of the ferroelectric field-effect transistor in advanced microelectronics. A ferroelectric field-effect transistor combines a ferroelectric material with a semiconductor in a transistor structure. In doing so, it merges logic and memory functionalities at the single-device level, delivering some of the most pressing hardware-level demands for emerging computing paradigms. Here, we examine the potential of the ferroelectric field-effect transistor technologies in cur- rent embedded non-volatile memory applications and future in-memory, biomimetic and alternative computing models. We highlight the material- and device-level challenges involved in high-volume manufacturing in advanced technology nodes (≤10 nm), which are reminiscent of those encountered in the early days of high-K-metal-gate transistor development. We argue that the ferroelectric field-effect transistors can be a key hardware component in the future of computing, providing a new approach to electronics that we term ferroelectronics.

· lower than that in STT -MRAM, RRAM and PCM and is within an order of magnitude of that of eSRAMs. Third, the tran sistor action in FEFETs, which is not available in other two terminal memories, allows not only for fast, non -destructive read but also
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NATure elecTroNIcS | VOL 3 | OCTObEr 2020 | 588597 | www.nature.com/natureelectronics 593 Program pulse Erase pulse Gate P IL p-Si Gate P IL p-Si Ferroelectric Ferroelectric EF e (1) (2) (3) (1) e Ec Ei Ev Ec (2) (6) Ei EF EF Ev (4) (5) + h+
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Fig. 5 | origin of endurance limitation in ferroelectric field-effect transistors. Energy band diagrams of the gate metalferroelectricILsemiconductor cross-section in an FEFET during program and erase cycles are shown. In both cases, the band diagrams correspond to the initial epochs during which the polarization has not yet switched in response to the voltage pulse. e and h+ represent electrons and holes, respectively. EF, Ec, Ev and Ei refer to the Fermi level (of either the semiconductor or the gate metal), the conduction band edge, the valence band edge and the intrinsic Fermi level of the semiconductor, respectively. The arrows in blue and red represents electron and hole transport, respectively, through the gate stack. The curly, vertical lines represent impact ionization processes. Different processes that are potentially responsible for FEFET degradation are denoted by6064: (1) electron injection from the cathode; (2) electron trapping in the bulk, the interface and the grain b
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Continued program and erase operations lead to charge trapping and trap generation in and degradation of the quality of the gate dielectric stack resulting in a progressive shift of the threshold voltages and a gradual narrowing of the memory window.
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